1. Field of the Invention
The present invention relates to a monitor, and more particularly to a CRT protective circuit for eliminating spots in accordance with a mute signal during the power off or mode converting operation.
2. Description of the Prior Art
Once a power switch of a general monitor is on, a cathode of an electron gun is heated and electron beam is emitted from the heated cathode. Then, the emitted electron beam collides into a phosphor layer to produce a spot.
This spot is deflected right to left in accordance with a deflection signal to form a raster, and brightness of the spot is changed to constitute a picture.
In more detail, the quantity of electron radiated from a cathode is controlled in accordance with the quantity of current flowing through a flyback transformer, and the brightness of the spot is determined in accordance with the quantity of the controlled electron. Also, the greater negative voltage supplied to a grid terminal is, the smaller quantity of electron is emitted from the cathode to make the picture dark.
Meantime, when the power switch of the monitor is off or mode is converted, a muting operation is performed at the initial time. This muting operation is for supplying a voltage which is lower than a voltage for normally operating respective circuits, e.g., a horizontal deflection circuit, a vertical deflection circuit, a video processor and a heater. A mute signal for executing the muting operation is generated from a microprocessor in accordance with an input of horizontal and vertical sync signals.
In other words, from the microprocessor, a mute signal of a low potential level, e.g., of about zero volt, is produced during the normal operation of respective circuits, and a mute signal of a high potential level, e.g., of about 5 volts, is provided for a predetermined time period in case of the power off or mode conversion state. This mute signal of high potential level lowers a voltage of the grid terminal. Therefore, the quantity of electron emitted from the cathode to the phosphor layer is decreased to make the spot be dimmed, thereby darkening the picture.
The monitor is generally furnished with a CRT protective circuit for protecting the CRT from the spot produced during the on/off operation of the power switch and mode converting operation, and such a CRT protective circuit includes a spot killer circuit and a muting circuit.
The conventional CRT protective circuit is constructed as shown in FIGS. 1 and 2.
In FIG. 1, a reference numeral 10 denotes a high voltage generating section for generating a high voltage resulting from the operation of a flyback transformer FBT and supplying the generated high voltage to a grid terminal G1 of a CRT. A reference numeral 20 denotes a microprocessor which provides a mute signal OUT1 for controlling the brightness of the spot in accordance with externally-provided horizontal and vertical sync signals Hs and Vs and a suspend signal OUT2 for eliminating the spot.
A reference numeral 30 denotes a mute signal processing section for controlling the brightness of the spot by controlling the magnitude of an input voltage of grid terminal G1 in accordance with mute signal OUT1; and 40 is a spot killer section for eliminating the spot by controlling the input voltage of grid terminal G1 in accordance with suspend signal OUT2.
The construction of the CRT protective circuit will be described more specifically with reference to FIG. 2 hereinbelow. High-voltage generating section 10 includes a diode 11 for biasing an output voltage of flyback transformer FBT and a capacitor 12 for flattening an output voltage of diode 11.
When being described in more detail, the mute signal processing section 30 is formed as follows. An emitter side of a transistor 32 which is switched in accordance with mute signal OUT1 supplied via a resistor 31 is connected with a resistor 33 for controlling the quantity of output current of transistor 31. The other side of resistor 33 is connected to an input terminal of power supply Vcc1, of about 5 volts. A collector side of transistor 32 is connected to a base side of a transistor 34 which is switched in view of the switching status of transistor 32, and a diode 35 for hindering the input voltage supply of grid terminal G1 toward an emitter of transistor 34 is connected between the emitter side of transistor 34 and grid terminal G1. A collector side of transistor 34 is connected to an output side of capacitor 12 of high voltage generating section 10. Between the collector side of transistor 34 and grid terminal G1, resistors 36 and 37 are connected in parallel for dividing an output voltage of capacitor 12 of high voltage generating section 10 in accordance with the switching status of transistor 34, and then supplying the divided voltage to grid terminal G1.
On the other hand, in describing the construction of spot killer section 40 in more detail, a collector side of a transistor 42 which is switched in accordance with suspend signal OUT2 supplied via a resistor 41 is connected with a resistor 43 which controls output current of transistor 42. The other side of resistor 43 is connected with an input terminal of a power supply Vcc2 of about 24 volts.
The collector side of transistor 42 is also connected with a base side of a transistor 44 which is switched in accordance with the switching status of transistor 42, and a collector side of transistor 44 is connected with a base side of a transistor 45 which is switched in accordance with the switching status of transistor 44. A resistor 46 for controlling output current of transistors 44 and 45 is connected between an emitter side of transistor 44 and collector side of transistor 44, and one side of resistor 46 is connected with an input terminal of a power supply Vcc3 of about 200 volts. An emitter side of transistor 45 is connected with a capacitor 47 which charges/discharges power supply Vcc3 in accordance with the switching status of transistor 45, and an output side of capacitor 47 is connected with an anode of a diode 48 which prevents the supply of an output voltage of capacitor 47 to a ground. An output side of capacitor 47 is connected with a resistor 49 which biases the output voltage of capacitor 47 to supply it to grid terminal G1. An emitter side of transistor 42, the other side of resistor 46 and a cathode of diode 48 are grounded.
The above enumerated conventional CRT protective circuit is operated and effected as below.
The high voltage of flyback transformer FBT is supplied diode 11 of high voltage generating section 10 to be subjected to shaping and the shaped high voltage is supplied to capacitor 12 which then flattens the shaped high voltage. Here, the flattened high voltage is approximately -80 volts.
When the monitor is in a normal mode, microprocessor 20 provides mute signal OUT1 of low level which is in turn supplied to transistor 32 via resistor 31. Transistor 32 is then switched under the turn-on state to provide a switching signal of high level.
The switching signal of high level is supplied to transistor 33 which becomes switched in the turn-off state. Accordingly, the output voltage of capacitor 12 is supplied to resistors 36 and 37 to be divided in resistors 36 and 37, and the divided voltages are supplied to grid terminal G1. At this time, the divided voltage is approximately -60 volts.
However, mute signal OUT1 goes to the high level when the power switch is turned off or mode is converted, and mute signal OUT1 of high level is supplied to transistor 32 via resistor 31. Transistor 32 then is switched in the turn-off state to provide the switching signal of low level.
The switching signal of low potential level is supplied to transistor 33 which thus is switched in the turn-on state. Accordingly, the output voltage of capacitor 12 is supplied to grid terminal G1 via transistor 34 and diode 35, and the supply voltage of grid terminal G1 is approximately -80 volts, which is almost the same as the output voltage of capacitor 12.
Briefly, while the power switch is turned off or mode is converted, the high voltage of grid terminal G1 is lowered from -60 volts to -80 volts according to mute signal OUT1 of microprocessor 20, thereby darkening the picture.
Especially, when the power switch is turned off and the heated cathode of the CRT is not thoroughly cooled down, an electrostatic capacitance is left between an inner conductive layer and an outer conductive layer of the CRT. Then, the electron emitted from the cathode due to the remaining electrostatic capacitance continuously collides into the phosphor layer to create the spots.
However, since the deflection circuit is not operated, the electrons emitted onto the phosphor layer are forcibly moved toward the central portion of the phosphor layer continuously to severely damage the central portion of the phosphor layer. Due to this fact, spot killer circuit 40 is additionally connected to the CRT since the muting operation cannot decrease the damage upon the phosphor layer. Spot killer circuit 40 functions for lowering the high voltage of grid terminal G1, and the spot becomes dimmed by the lowered high voltage.
More specifically, when the monitor is of the normal mode, microprocessor 20 provides suspend signal OUT2 of high level. Then, suspend signal OUT2 of high level is supplied to transistor 42 via resistor 41, transistor 42 is switched in the turn-on state, and power supply Vcc2 is supplied to the emitter side of transistor 42 via resistor 43. Consequently, transistor 42 provides the switching signal of low level.
The switching signal of low level is supplied to transistor 44 which is in turn switched in the turn-off state to provide the switching signal of high level. The switching signal of high level is supplied to transistor 45 which is then switched in the turn-on state. Accordingly, power supply Vcc3 is supplied to capacitor 47 via transistor 45, and capacitor 47 charges power supply Vcc3.
Once the power switch is switched in the turn-off state, suspend signal OUT2 is transited to the low level, and suspend signal OUT2 of low level is supplied to transistor 42 via resistor 41. Also, transistor 42 is switched in the turn-off state, and power supply Vcc2 is supplied to the base side of transistor 44 via resistor 43. As the result, transistor 42 provides the switching signal of high level.
The switching signal of high level is supplied to transistor 44 which is thus switched in the turn-on state to provide the switching signal of low level. The switching signal of low level is supplied to transistor 45 which is then switched in the turn-off state. By doing so, power supply Vcc3 becomes grounded via resistor 46. Here, the charging voltage of capacitor 47 is supplied to diode 48 to be inverted to have the backward potential, and the inverted charging voltage of capacitor 47 is supplied to grid terminal G1 via resistor 49. Hence, the potential of grid terminal G1 is lowered with the spot dimming.
That is, in the normal mode, microprocessor 20 provides mute signal OUT1 of low level and suspend signal OUT2 of high level. Also, when the power switch is switched in the turn-off state, microprocessor 20 provides mute signal OUT1 of high level and suspend signal OUT2 of low level. By these operation, the potential of grid terminal G1 is lowered to thoroughly weaken the spot.
However, during the mode converting operation, since microprocessor 20 provides mute signal OUT1 of high level and suspend signal OUT2 of high level, the potential of grid terminal G1 becomes -80 volts. Because of the potential of grid terminal G1, the spot cannot be thoroughly weakened.